System-Level HardwarelSoftware Trade-offs
نویسنده
چکیده
Achieving timely and comprehensive functional design verifi-cation is a ubiquitous problem in electronics. This panel offers per-spectives on verification from designers of cardiac pacemakers,communications satellites, compute servers, networking equip-ment, and IP. The panelists will begin by dissecting the bottlenecks in theirverification processes. For example, are simulators too slow? Or dotest vector generation and coverage analysis consume the mosttime? The panelists will present their ideas for new EDA productswhich might accelerate verification. Finally, the panelists will dis-cuss what compromises they would accept in order to achieve thisacceleration. Would they learn a new HDL? Restrict their designstyles? Forsake legacy designs?
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